
India’s semiconductor strategy: building capacity from design to packaging
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The annual budget includes targeted tax relief and other incentives to accelerate downstream rare‑earth refining and magnet production, backed by a larger capital‑expenditure push. Success will hinge on clear eligibility rules, performance‑linked conditions, coordinated state corridors for processing, and investments in reagents, power and skilled labour.
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India’s technology minister said the country is targeting the commercial launch of domestically branded smartphones within roughly 12–18 months, citing a maturing electronics supply chain and recent wafer‑fabrication investments. The plan pairs that ambition with a pragmatic focus on assembly, testing and packaging (OSAT) capacity and will likely rely on external SoCs and ODM partnerships in the near term while local design and cleanroom skills are developed.

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Semiconductor Industry Faces Rising Climate Costs from AI Memory Rush
A surge in demand for AI-optimized memory (HBM and high-performance DRAM) is driving wafer-starts and higher per-die energy intensity, forcing fabs to expand capacity and shift production into regions with varied grid carbon intensity. That reallocation, combined with steep DRAM price moves and longer contract horizons, will raise scope-2 exposure and near-term emissions-related operating costs while reshaping procurement, capex and site-selection economics.
India’s Budget Ignites Rally in Electronics Manufacturers as Policy Push Tests Localisation
India’s federal budget doubled down on policies to accelerate local electronics production, prompting an immediate rally in listed assemblers and suppliers. Complementary industry moves — new OSAT facilities coming online and a government push for home-branded smartphones — sharpen the near-term opportunity but leave success dependent on workforce readiness, critical imports and timely incentive delivery.
India lengthens startup runway and backs deep tech with public capital
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TSMC to build 3nm AI-focused fabs in Kumamoto, accelerating Japan’s chip strategy
TSMC will manufacture 3-nanometer chips at its second Kumamoto facility to meet structurally stronger AI-related demand, a decision underpinned by recently improved profitability and customer-verified orders from hyperscalers. The move broadens TSMC’s geographic footprint, dovetails with Tokyo’s subsidy push and wider U.S.–Taiwan trade and investment dynamics, and heightens both industrial opportunity and execution risk tied to ramping yields and tool supply.
India’s 2026-27 Budget doubles down on infrastructure spending while tightening fiscal targets
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